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We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip with a family of GasP circuits, making use of automatic transistor sizing and automatic layout generation. Results from simulations show that the chip will function correctly at speeds of up to 1.6 GHz in a 180 nm TSMC process. The cycle time of our stack chip is about 7 FO4 delays and is independent of the number of data items in the stack and the data width. The energy consumption per stack operation depends on the sequence of stack operations, but grows slowly with the number of data items in the stack.