A parallel programmable energy-efficient architecture for computationally-intensive DSP systems

An architecture that is well matched to DSP system workloads, enables high-throughput and high energy-efficiency, and is well suited for advancing VLSI fabrication technologies is presented. These processing systems consist of large numbers of simple uniform programmable processing elements communicating asynchronously through a configurable 2D mesh network that connects adjacent processors at full clock rates. Early estimates predict an area density of 0.15 mm/sup 2/ per processor in 0.13 /spl mu/m CMOS. Results from mapping a 16-tap FIR filter over 85 design configurations show a factor of 9 variation in throughput per processor and validate the efficiency of the proposed processor granularity.