Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor

This paper explores the area-throughput trade-off for an ASIC implementation of the advanced encryption standard (AES) algorithm in a 0.18 /spl mu/m CMOS technology. Three different pipelined implementations of the AES algorithm are presented which provide a throughput range between 15.7 to 77.6 Gbits/s with an area cost of 116 to 473 Kgates. Therefore, the AES algorithm in the counter mode of operation can be used to generate cryptographically secure pseudorandom numbers at a throughput rate of multiten Gbits/s. Thus it becomes available for encryption on an optical link.