A high resolution, stictionless, CMOS compatible SOI accelerometer with a low noise, low power, 0.25 /spl mu/m CMOS interface

The implementation and characterization of a high sensitivity silicon-on-insulator (SOI) capacitive microaccelerometer with sub-25 /spl mu/g resolution is presented. The in-plane accelerometers were fabricated on 40 /spl mu/m thick SOI substrates using a two-mask, dry-release low temperature process comprising of three plasma etching steps. The fabricated devices were interfaced with a high resolution, low noise and low power switched-capacitor integrated circuit (IC) fabricated in a 2.5 V 0.25 /spl mu/m N-well CMOS process. The measured sensitivity is 0.2 pF/g and the output noise floor is 20 /spl mu/g//spl radic/Hz. The total power consumption is 3 mW.