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The paper deals with a tuning method to reduce warpage of Printed Circuit Boards (PCBs). There are three main processes involved in this method: calculating effective properties of PCBs with simple regular electric artworks, using three-dimensional (3D) Finite Element (FE) modeling; fitting simplified expressions to the results from these analyses; and developing two-dimensional (2D) FE models of a whole PCB, with arbitrarily complicated artwork, using the simplified expressions. These three processes were used to estimate the warpage of a production PCB. Iterative searches, or optimization, were used to change trace width, spacing, etc. in order to reduce the warpage. It was demonstrated that by slightly varying trace widths and spacings in the PCB, warpage could be reduced approximately by a factor of five.