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Verification of high-assurance system designs before they are fabricated on chips reduces time and money costs related to chip testing. Test benches, which are used in simulating and verifying VHDL designs, need to perform efficiently and effectively. Test automation through the automated generation of test patterns increases the efficiency and effectiveness of behavioral verification. We apply heuristic rules to generate test cases for VHDL behavioral designs. Their aim is to increase code coverage. They are based on control-flow and data-flow analysis. We applied the RUle-BAsed Software TEsting Method (RUBASTEM) to small, medium, and large examples. The results of RUBASTEM showed that this method achieves higher branch coverage.