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Fault tolerance for future COTS hardware

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1 Author(s)
Shubu Mukherjee ; Massachusetts Microprocessor Design Center, Intel Corp., Shrewsbury, MA, USA

Summary form only given. With each technology generation, we are experiencing an increased rate of cosmically-induced soft errors in our microprocessor chips. The advent of such high levels of soft error protection on microprocessors chips will necessitate revisiting the design of highly dependable systems, such as those used in space, built with COTS (commodity off-the-shelf) hardware. However, given that processors would internally deal with soft errors, it is not clear if highly dependable systems would need to additionally implement off-chip lockstepping to cope with permanent faults. Worse, implementing off-chip lockstepping at extremely high speeds, such as tens of gigahertz, is extremely difficult. Hence, designers may need to consider alternate techniques, such as processor sparing, to deal with permanent faults in processor chips used in mission-critical systems.

Published in:

Dependable Computing, 2004. Proceedings. 10th IEEE Pacific Rim International Symposium on

Date of Conference:

3-5 March 2004