Skip to Main Content
We present a theory of one-dimensional layout compaction that is based on the graph theoretic approach used in such compacters as reported in , , , and . Compaction here consists of two steps. In the first stage, a directed graph is extracted from the layout. In the second stage, compaction is performed by solving a single-source shortest path problem on this graph. The paper presents new efficient algorithms and/or heuristics for the first stage of the compaction process. A compacter based on the framework presented here that incorporates the algorithms described is a powerful tool that can easily be tailored to specific applications. It allows a tradeoff between the space and runtime performance of the compacter and the quality of the compaction.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:6 , Issue: 5 )
Date of Publication: September 1987