By Topic

Hierarchical Loose Routing for Gate Arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
K. Winter ; University of Karlsruhe, Karlsruhe, Germany ; D. A. Mlynski

In this paper, we present a new, quasi-parallel approach to the loose routing problem for gate array LSI design. It is based on a new modeling for the decomposition problem of each net using a compact net graph which maps sets of feed-throughs instead of individual ones. The loose routing is done by calculation of a minimum spanning tree in this net graph and by a proper embedding of the tree as a set of single-channel subnets and feed-throughs. Moreover, a hierarchical approach is proposed, leading to a quasi-parallel embedding of all nets. It also allows different routing priorities for single connections within multiterminal nets. The hierarchical loose routing concept presented here is implemented in the fully integrated gate array design system MEGA and has been successfully tested on several industrial design examples.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:6 ,  Issue: 5 )