By Topic

A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Banerjee, P. ; Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL, USA ; Abraham, J.A.

This paper proposes a new logical model for nMOS and CMOS circuits. Existing gate-level and switch-level models are limited in their ability to simulate MOS circuit behavior accurately when modeling physical failures. The model proposed in this paper is in the form of a multivalued algebra defined on a set of node states. The state of a node is represented as a pair <a,b> where "a" specifies the condition of a node and "b" specifies the logic level: There are five conditions and five logic levels. The assignment of node states is done dynamically during the process of logic simulation. The rules of the algebra are used to derive state tables that model the behavior of transistors. Our general model of a transistor allows for strong interactions between all three terminals of a transistor. This enables us to model the effects of physical failures such as a short between the gate and drain of a transistor. A simulation algorithm based on the algebra is discussed, and techniques for simulating physical failures in MOS circuits using the algebra are indicated.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:4 ,  Issue: 3 )