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We present a new algorithm for functional test generation of VLSI systems. This algorithm for functional test generation for each testable register-transfer (RT) level fault defined in our established fault model. The technique developed is appropriate for test generation in top-down Computer-Aided Design process. The development of the algorithm is based on two foundations: the RT-level fault model and symbolic execution technique. A well-defined RT-language for the functional representation of a digital system is described. Based on this language, the RT-level fault modeling and fault collapsing analysis are performed. The fault model is established to lay an analytical foundation for the investigation of faulty behavior among RT-level fault types. The RT-level symbolic execution technique is used to derive test patterns during test generation. Major problem areas are defined and appropriate solutions are presented. The whole test generation process is divided into three stages: preprocess, the S-algorithm, and post-process. "Divide and conquer" principle is used throughout the test generation process for systematic problem solving. The S-algorithm is the heart of the overall algorithm. It performs test pattern generation based on the reduced fault model using machine symbolic execution. This test generation algorithm has been implemented in PASCAL on IBM 370/168.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:4 , Issue: 3 )
Date of Publication: July 1985