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Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits

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1 Author(s)
W. Maly ; Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA, USA

In this paper, a modeling technique, describing IC manufacturing yield losses in terms of parameters characterizing lithography related point defects and line registration errors, is presented. Optimization of geometrical design rules, evaluation of VLSI IC artwork, and maximization of the wafer yield are discussed as examples illustrating applications and advantages of the proposed modeling technique.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:4 ,  Issue: 3 )