By Topic

A 14-bit delta-sigma ADC with 8× OSR and 4-MHz conversion bandwidth in a 0.18-μm CMOS process

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ruoxin Jiang ; Maxim Integrated Products, Hillsboro, OR, USA ; T. S. Fiez

A 14-bit 8× oversampling delta-sigma (ΔΣ) analog-to-digital converter (ADC) for wide-band communication applications has been developed. By using a novel architecture, a high maximum out-of-band quantization noise gain (Qmax) is realized, which greatly improves the SNR and tonal behavior. The ADC employs a fifth-order single-stage structure with a 4-bit quantizer. It achieves 82-dB SNDR and 103-dB SFDR at 4-MHz conversion bandwidth with a single 1.8-V power supply.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:39 ,  Issue: 1 )