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On interconnecting circuits with multiple scan chains for improved test data compression

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2 Author(s)
Pomeranz, I. ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Reddy, S.M.

We show that when a scan design consists of interconnected circuits, test data volume reductions can be achieved by connecting the scan chains of adjacent circuits appropriately. We formulate this problem as a problem of finding a permutation of the scan chains of one circuit with respect to another so as to minimize the number of different scan vectors required for testing both circuits. We propose a procedure for solving this problem, and present experimental results.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference:

2004