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Adaptive error protection for energy efficiency

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4 Author(s)
Lin Li ; Microsyst. Design Lab., Pennsylvania State Univ., USA ; N. Vijaykrishnan ; M. Kandemir ; M. J. Irwin

With dramatic scaling in feature sizes, noise resilience is becoming one of the most important design parameters, similar to performance and energy efficiency. Noise resilience is particularly problematic in long on-chip buses of complex single chip systems such as on-chip multiprocessors. While one might opt to employ a very powerful error protection scheme, this may not be very energy efficient as noise behavior typically varies over time. In this paper, we propose an adaptive error protection scheme for energy efficiency, where the type of the coding scheme is modulated dynamically. The idea behind this strategy is to monitor the dynamic variations in noise behavior and use the least powerful (and hence the most energy efficient) error protection scheme required to maintain the error rates below a pre-set threshold. Our detailed experimental results obtained through simulation show that this adaptive strategy achieves the same level of error protection as the most powerful strategy experimented, without experiencing the latter's energy inefficiency. Based on our results, we recommend system designers to adopt adaptive protection schemes in environments where both energy and reliability are important.

Published in:

Computer Aided Design, 2003. ICCAD-2003. International Conference on

Date of Conference:

9-13 Nov. 2003