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We describe a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors. Under this approach, the scan-in, scan-select, and scan-out lines are treated as conventional primary inputs or primary outputs of the circuit. As a result, limited scan operations, where scan chains are shifted a number of times smaller than their lengths, are incorporated naturally into the test sequences generated by this approach. This leads to very aggressive compaction, resulting in test sequences with the lowest known test application times for benchmark circuits. The resulting test sequences can be applied using conventional test application schemes that support limited scan operations.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:22 , Issue: 12 )
Date of Publication: Dec. 2003