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Between-core vector overlapping for test cost reduction in core testing

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5 Author(s)
T. Shinogi ; Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan ; Y. Yamada ; T. Hayashi ; T. Yoshikawa
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This paper proposes a novel method, called "between-core vector overlapping", for parallel core testing of an SoC consisting of full-scanned cores. This method uses small number of input pins in the parallel core testing. An "over-lapped vector" obtained by overlapping all the vectors for all the core is supplied to all the cores in common for parallel core testing. Two methods for short overlapped vectors, "invert overlapping" and "split overlapping", are presented. The impact of further reduction in the number of input pins is also reported.

Published in:

Test Symposium, 2003. ATS 2003. 12th Asian

Date of Conference:

16-19 Nov. 2003