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Code compression for the embedded ARM/THUMB processor

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2 Author(s)
Xianhong Xu ; Fac. of Eng. & Design, Univ. of Bath ; Jones, S.

Previous code compression research on embedded systems was based on typical RISC instruction code. THUMB from ARM Ltd is a compacted 16-bits instruction set showing a great code density than its original 32-bits ARM instruction. Our research shows that THUMB code is compressible and a further 10-15% code size reduction on THUMB code can be expected using our proposed new architecture - code compressed THUMB processor. In our proposal, level 2 cache or additional RAM space is introduced to serve as the temporary storage for decompressed program blocks. A software implementation of the architecture is proposed and we have implemented a software prototype based on ARM922T processor, which runs on the ARMulator

Published in:

Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2003. Proceedings of the Second IEEE International Workshop on

Date of Conference:

8-10 Sept. 2003