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Verification pattern (VP) is a new technique to test embedded systems rapidly, and it has been used to test industrial safety-critical embedded systems successfully. The key concept of this approach is to classify system scenarios into patterns, and use the same code template to test all the scenarios of the same pattern. In this way, testing effort can be greatly reduced. This paper extends VPs so that they can fully interoperate with a formalized scenario model ACDATE. In this way, various static and dynamic analyses can be performed on system scenarios as well as on system patterns. Furthermore, this paper provides a mapping from system scenarios into temporal logic expressions. In this way, a practitioner can specify system constraints in scenarios, and follow the mapping to obtain the temporal logic expressions easily to perform formal model checking. This paper also provides an OO framework to support automated test script development from VPs. In this way, VPs can be used in an integrated process where both semi-formal analyses and formal techniques can be used together to develop mission-critical embedded applications.
Date of Conference: 3-6 Nov. 2003