By Topic

A 13.3-Mb/s 0.35-μm CMOS analog turbo decoder IC with a configurable interleaver

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
V. C. Gaudet ; Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, Alta., Canada ; P. G. Gulak

Circuits and an IC implementation of a four-state, block length 16, three-metal one-poly 0.35-μm CMOS analog turbo decoder with a fully programmable interleaver are presented. The IC was tested at 13.3 Mb/s, has a 1.2 μs latency, and consumes 185 mW on a single 3.3-V power supply, resulting in an energy consumption of 13.9 nJ per decoded bit, thus reducing the energy consumption by 70% relative to existing digital turbo decoders. The core area is 1131.2×1257.9 μm2. The addition of swinging buffers could triple the speed and reduce the latency with minimal increase in power consumption by overlapping storage and decoding phases. Mismatch simulations show that the circuits will be viable for decoder lengths up to a few hundred information bits.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:38 ,  Issue: 11 )