Skip to Main Content
An 802.11a compliant medium access control (MAC) and physical layer (PHY) processing chip has been successfully fabricated in 0.18-μm CMOS. Thirty million transistors are integrated on a 10.91×10.91 mm2 die housed in a 361-pin PFBGA. The MAC functions are fully implemented by firmware on an embedded 32-b RISC processor, 4-Mb SRAM, and hardware acceleration logic. The PHY supports a complete set of data rates up to 54 Mb/s. Immediate PS-Poll response is realized by the hardware-centric architecture, which can reduce the power consumption of the baseband chip and external RF/IF chips by 29% in power-save mode. The newly developed hybrid automatic gain control circuit can adjust receive signal strength to ±1 dB within 2 μs. Required carrier-to-noise ratio is lower than 4.9 dB at 6-Mb/s data rate and 21.7 dB at 54-Mb/s data rate.