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A 10-GHz global clock distribution using coupled standing-wave oscillators

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4 Author(s)
F. O'Mahony ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; C. P. Yue ; M. A. Horowitz ; S. S. Wong

In this paper, a global clock network that incorporates standing waves and coupled oscillators to distribute a high-frequency clock signal with low skew and low jitter is described. The key design issues involved in generating standing waves on a chip are discussed, including minimizing wire loss within an available technology. A standing-wave oscillator, which is a distributed oscillator that sustains ideal standing waves on lossy wires, is introduced. A clock grid architecture comprised of coupled standing-wave oscillators and differential low-swing clock buffers is presented, along with a compact circuit model for networks of oscillators. The measured results for a prototyped standing-wave clock grid operating at 10 GHz and fabricated in a 0.18-μm 6M CMOS logic process are presented. A technique is proposed for on-chip skew measurements with subpicosecond precision.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:38 ,  Issue: 11 )