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We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use the power profile of nonembedded cores to find the best mix of their test pattern subsets that satisfy the power and/or time constraints. An MILP formulation is presented to globally perform the power-time tradeoff and produce the SoC test schedule. Many constraints including peak/average power of cores, time/sequencing requirements, and ATE pin limitation are also incorporated within this formulation.
Date of Conference: 13-15 Oct. 2003