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Fully differential receiver chipset for 40 Gb/s applications using GaInAs/InP single heterojunction bipolar transistors

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6 Author(s)
Kiziloglu, K. ; Intel Commun. Group, Intel Corp., Santa Clara, CA, USA ; Seetharaman, S. ; Glass, K.W. ; Bil, C.
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Advent of multimedia applications, which require data links with ever-increasing capacity, is necessitating highspeed optical communication systems and driving research and development for high-speed ICs operating at 40 Gb/s. These optical fiber communication systems require high performance and low power chipsets, which incorporate useful service functions. We report on the design and characterization of a fully-differential 40 Gb/s receiver chipset, which includes a transimpedance amplifier and a limiting amplifier for SONET/SDH STS-768/STM-256 applications. The chipset is realized using a GaInAs/InP single heterojunction bipolar transistor (SHBT) process with a nominal fT>150GHz and fmax>180GHz.

Published in:

Computer Design, 2003. Proceedings. 21st International Conference on

Date of Conference:

13-15 Oct. 2003