Skip to Main Content
Effective prefetching of data from a lower memory hierarchy to higher level is a helpful way to combat the increasing memory latency that impedes the performance improvement. This paper presents a hardware-based prefetching technique to alleviate load misses caused by irregular access patterns common in linked-list structures. Different from previous works we identify a pointer load using its architecture source register. A table called target register bitmap (TRB) is maintained. By looking up this table we can identify if a load is a pointer load. We remember the base addresses of consumer load operations in a cache and prefetch the data pointed by speculative virtual addresses to a prefetch buffer, which is smaller than the data cache. Whenever a load is encountered, both the prefetch buffer and the data cache are looked up. SPEC2000 and Olden benchmarks are used to evaluate this method. This technique is able to predict accurately over 80% of the pointer load address. A system using this technique having 8KB LI data cache plus a 1KB address cache and a 1KB prefetch buffer gives an average of around 6% performance improvement over a system with 16KB LI data cache.
Date of Conference: 13-15 Oct. 2003