Referenced Items are not available for this document.
We present a mixed-mode delay-locked loop (DLL) architecture intended for multiple-phase clock generation. In contrast to analog DLLs, the proposed architecture allows for clock-gating; moreover, circuit simulations indicate that its performance (in terms of maximum frequency, frequency range, and low-speed power dissipation) is superior to that of a previously-reported, purely digital DLL.
Published in:
Computer Design, 2003. Proceedings. 21st International Conference on
Date of Conference: 13-15 Oct. 2003
- Page(s):
- 261 - 263
- ISSN :
- 1063-6404
- Print ISBN:
- 0-7695-2025-1
- INSPEC Accession Number:
- 7946636
- Digital Object Identifier :
- 10.1109/ICCD.2003.1240904
- Product Type:
- Conference Publications
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