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Specifying and verifying systems with multiple clocks

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3 Author(s)
Clarke, E.M. ; Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Kroening, D. ; Yorav, K.

Multiple clock domains are a challenge for hardware specification and verification. We present a method for specifying the relations between multiple clocks, and for modeling the possible behaviors. We can then verify a hardware design assuming that the clocks meet these constraints. We implement our ideas in the context of SAT based bounded model checking (BMC), using ANSI-C programs to specify the functional behavior of the design.

Published in:

Computer Design, 2003. Proceedings. 21st International Conference on

Date of Conference:

13-15 Oct. 2003