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The essence of existing methods to simulate crosstalk pulse faults in sequential circuits is the use of logic waveform on each line in the circuit. Explicitly keeping track of timing information is costly in terms of memory usage and computational effort. We propose and develop a novel approach to the simulation of crosstalk pulse faults due to coupling between aggressor lines and victim (flip-flop) clock lines. Our algorithm extends existing ideas fundamental to logic event-driven simulation to crosstalk faults excitation and fault grouping. In addition, our simulator treats issues related to timing in a more precise manner. Experimental results on ISCAS '89 benchmark circuits show extraordinary improvement on all fronts, including CPU time, fault coverage, and memory usage.