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Miss rate prediction across all program inputs

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3 Author(s)
Y. Zhong ; Dept. of Comput. Sci., Rochester Univ., NY, USA ; S. G. Dropsho ; C. Ding

Improving cache performance requires understanding cache behavior. However, measuring cache performance for one or two data input sets provides little insight into how cache behavior varies across all data input sets. We use our recently published locality analysis to generate a parameterized model of program cache behavior. Given a cache size and associativity, this model predicts the miss rate for arbitrary data input set sizes. This model also identifies critical data input sizes where cache behavior exhibits marked changes. Experiments show this technique is within 2% of the hit rate for set associative caches on a set of integer and floating-point programs.

Published in:

Parallel Architectures and Compilation Techniques, 2003. PACT 2003. Proceedings. 12th International Conference on

Date of Conference:

27 Sept.-1 Oct. 2003