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Efficient resource management during instruction scheduling for the EPIC architectures

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6 Author(s)
D. -Y. Chen ; Intel Labs., Intel Corp., Santa Clara, CA, USA ; L. Liu ; Chen Fu ; Shuxin Yang
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Effective and efficient modelling and management of hardware resources have always been critical toward generating highly efficient code in optimizing compilers. The instruction templates and dispersal rules of the EPIC architecture add new complexity in managing resource constraints to instruction scheduler. We extended a finite state automaton (FSA) approach to efficiently manage all key resource constraints of an EPIC architecture on-the-fly during instruction scheduling. We have fully integrated the FSA-based resource management into the instruction scheduler in the Open Research Compiler for the EPIC architecture. Our integrated approach shows up to 12% speedup on some SPECint2000 benchmarks and 4.5% speedup on average for all SPECint2000 benchmarks on an Itanium machine when compares to an instruction scheduler with decoupled resource management. In the meantime, the instruction scheduling time of our approach is reduced by 4% on average.

Published in:

Parallel Architectures and Compilation Techniques, 2003. PACT 2003. Proceedings. 12th International Conference on

Date of Conference:

27 Sept.-1 Oct. 2003