Referenced Items are not available for this document.
PLL clock generators are designed for a third-generation NetBurst™ processor implemented in a 90nm CMOS process. A cascade configuration offers improved jitter attenuation and facilitates a wide synthesis range. Parameter design takes into account a dual-sloped VCO control. A new charge pump topology offers superior symmetry.
Published in:
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Date of Conference: 2003
- Page(s):
- 422 - 504 vol.1
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-7707-9
- INSPEC Accession Number:
- 7791710
- Digital Object Identifier :
- 10.1109/ISSCC.2003.1234366
- Product Type:
- Conference Publications
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