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A 400MT/s 6.4GB/s multiprocessor bus interface

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7 Author(s)
Muljono, H. ; Intel Corp., Santa Clara, CA, USA ; Beomtaek Lee ; Tian, K. ; Wang, Y.E.
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A 0.13/spl mu/m 1.2V GTL bus interface with compensated slew rate and termination achieves 400MT/s at a 6.4GB/s data rate in a 5-load MP environment. Packaged on an FCBGA and interposer with 5:1:4 signal to power and ground ratio and routed on 12mm 45/spl Omega/ traces, the interface incorporates I/O timing self test supported by a DLL and an interpolator with 25ps peak-to-peak jitter.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003

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