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A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination

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16 Author(s)
Ho Young Song ; Samsung Electron., Hwasung, South Korea ; Seong Jin Jang ; Jin Seok Kwak ; Cheol Su Kim
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For operating frequencies exceeding 500 MHz, the timing margin of the I/O interface is critical and requires the data input-output timing accuracy to be within 200 ps. To meet the requirement, the designed SDRAM adopts a digitally self-calibrated on-die-termination with linearity error of /spl plusmn/1% and achieves over 1.2 Gbps/pin stable operation by using window matching and latency control. The chip is fabricated in a 0.13 /spl mu/m triple-well DRAM process.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003