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A 144 Mb DRAM operates at a random cycle of 5.6 ns and is capable of producing data rates of 1.4 Gb/s/pin. The 121 mm/sup 2/ die is fabricated in a 0.13 /spl mu/m logic-based process. The cycle-time is achieved using an early-write sensing technique. Dynamic-precharge decoding and improved data-formatting circuits produce latencies of 5.0 ns.