A 3 A 20 MHz BiCMOS/DMOS power operational amplifier: a structural design approach

Design of a power op-amp using a structural design methodology is presented. The BiCMOS/DMOS op-amp features rail-to-rail output, 3 A maximum output current, adjustable current limit without delay, a class AB input stage with a 50 V//spl mu/s slew rate, and 100 dB open-loop gain with a 2 /spl Omega/ load. It consumes 50 mA from a single 7-16 V supply.