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A dual channel /spl Sigma//spl Delta/ ADC with 40MHz aggregate signal bandwidth

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5 Author(s)
A. Tabatabaei ; Atheros Commun., Sunnyvale, CA, USA ; K. Onodera ; M. Zargari ; H. Samavati
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A dual-channel /spl Sigma//spl Delta/ ADC has been integrated in 0.13/spl mu/m CMOS technology with an oversampling ratio of 4. The ADC employs a cascade of low-pass and band-pass modulators and achieves an aggregate quadrature signal bandwidth of 40MHz at a sampling frequency of 160MS/s and 54dB dynamic range while dissipating 175mW from a 2.5V supply.

Published in:

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Date of Conference:

13-13 Feb. 2003