A dual channel /spl Sigma//spl Delta/ ADC with 40MHz aggregate signal bandwidth

A dual-channel /spl Sigma//spl Delta/ ADC has been integrated in 0.13/spl mu/m CMOS technology with an oversampling ratio of 4. The ADC employs a cascade of low-pass and band-pass modulators and achieves an aggregate quadrature signal bandwidth of 40MHz at a sampling frequency of 160MS/s and 54dB dynamic range while dissipating 175mW from a 2.5V supply.