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A technique for nonlinearity self-calibration of DLLs

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5 Author(s)
Baronti, F. ; Dipt. di Ingegneria dell''Informazione, Univ. of Pisa, Italy ; Fanucci, L. ; Lunardini, D. ; Roncella, R.
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The on-chip nonlinearity self-calibration of a CMOS all-digital shunt-capacitor-based delay-locked delay-line is achieved by first measuring the nonlinearity of each delay-cell by means of a statistical test, and then individually correcting the cell delay mismatch according to the test results. An iterative calibration algorithm has been developed and a fully-digital circuit efficiently implementing the calibration procedure has been designed. Simulation results show the feasibility of the technique and a significant reduction of the delay-line maximum nonlinearity down to values that can be below 1%.

Published in:

Instrumentation and Measurement, IEEE Transactions on  (Volume:52 ,  Issue: 4 )

Date of Publication:

Aug. 2003

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