Referenced Items are not available for this document.
We proved that the hardware implementation of the proposed code and the new packet synchronization system was effectively realized by using a unique circuit configuration. A three-dimensional size-five coder and decoding-synchronization system was implemented on FPGA. The developed FPGA was applied to a high-speed MPEG communication device, which can transmit a movie signal of 20 Mbps.
Published in:
Information Theory, 2003. Proceedings. IEEE International Symposium on
Date of Conference: 29 June-4 July 2003
- Print ISBN:
- 0-7803-7728-1
- INSPEC Accession Number:
- 8555337
- Digital Object Identifier :
- 10.1109/ISIT.2003.1228489
- Product Type:
- Conference Publications
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