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High-speed error correcting code LSI with throughput of 5 to 48 Gbps

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3 Author(s)
Y. Hamasuna ; DDS Inc., Nagoya, Japan ; M. Hata ; I. Takumi

We proved that the hardware implementation of the proposed code and the new packet synchronization system was effectively realized by using a unique circuit configuration. A three-dimensional size-five coder and decoding-synchronization system was implemented on FPGA. The developed FPGA was applied to a high-speed MPEG communication device, which can transmit a movie signal of 20 Mbps.

Published in:

Information Theory, 2003. Proceedings. IEEE International Symposium on

Date of Conference:

29 June-4 July 2003