Referenced Items are not available for this document.
A method for interfacing synchronous blocks of logic with different local clocks is presented which introduces very little latency and avoids metastability. The method does not require stopping or stretching local clocks and enforces correct operation of a bundled data constraint for all but very wide data paths.
Published in:
University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial
Date of Conference: 30 June-2 July 2003
- Page(s):
- 342 - 343
- ISSN :
- 0749-6877
- Print ISBN:
- 0-7803-7972-1
- INSPEC Accession Number:
- 7937135
- Digital Object Identifier :
- 10.1109/UGIM.2003.1225761
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
