By Topic

Source/drain optimization of the dynamic-threshold DTMOS device in a 0.15 μm SOI embedded DRAM technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Burke, F. ; Dept. of Electr. & Comput. Eng., Boise State Univ., ID, USA ; Rambhatla, A. ; Zahurak, J. ; Parke, S.

This paper describes experimental results used to optimize the source/drain implant design of a dynamic threshold DTMOS n-channel device, fabricated within a low-cost 0.15 μm SOI CMOS System-On-Chip process, which also included high-density embedded DRAM. A shallower, lower dose S/D implant was found to lower the body resistance and DIBL, thus increasing the dynamic body effect. The DTMOS device design in this process was previously found to be superior to both grounded body (GB) and floating body (FB) operation, with Ion=56 uA/μm, Ioff=3 pA/μm, S=64 mV/dec, and Gm=1690 uS/μm at Vdd=1.0 V. This DTMOS device was also previously shown to have excellent analog and RF performance, with Fmax=32 GHz. These characteristics permit embedded ultra-low-voltage analog circuits and RF front-end circuits in combination with embedded DRAM cores for ultra-low-power, low-cost SOCs.

Published in:

University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial

Date of Conference:

30 June-2 July 2003