By Topic

Gate dielectric degradation effects on nMOS devices using a noise model approach

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
7 Author(s)
Lawrence, C.E. ; Dept. of Electr. & Comput. Eng., Boise State Univ., ID, USA ; Cheek, B.J. ; Lawrence, T.E. ; Kumar, S.
more authors

The effects of noise on gate oxide reliability were examined in nMOSCAPs. Noise is modeled as a voltage spike constructively interfering with a carrier signal. This data correlates to the noise model where device lifetime exponentially decreases with an increase in noise voltage. Noise voltages with the same magnitude as the carrier signal voltage decrease the lifetime by as much as three orders of magnitude. For noise that is one-fifth of the magnitude of the carrier signal voltage, an order of magnitude is observed. As interconnect spacing decreases, the probability of noise and capacitive coupling increases; therefore, the effect of noise on the lifetime of MOS devices may be of great concern.

Published in:

University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial

Date of Conference:

30 June-2 July 2003