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Testing oriented analysis of CMOS ICs with opens

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3 Author(s)
W. Maly ; Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA ; P. K. Nag ; P. Nigh

In a typical approach to VLSI testing, open faults are modeled by the transistor-stuck-open fault model or are not explicitly covered at all. It is shown that functional faults caused by opens, i.e. by regions with missing material, cannot be modeled well by a transistor stuck-open. It is also shown that the majority of opens which occur in CMOS static circuits manifest themselves as timing faults. The analysis of the behavior of a CMOS transistor with a floating gate indicates it acts as a weakly 'on' active load, and therefore an open gate cannot be detected by stuck-fault testing but could be detected by monitoring the static current through the power buses.<>

Published in:

Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on

Date of Conference:

7-10 Nov. 1988