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A low cost high performance register-controlled digital DLL for 1 Gbps/spl times/32 DDR SDRAM

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5 Author(s)
Jong-Tae Kwak ; Memory R&D Div., Hynix Semicond. Inc., Kyoungki, South Korea ; Chang-Ki Kwon ; Kwan-Weon Kim ; Seong-Hoon Lee
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A low cost high performance register-controlled digital delay-locked loop (DLL) that has novel resolution-enhancing structure with inherent duty cycle correction capability was developed for 1 Gbps/spl times/32 DDR SDRAM. Experimental results in a 0.13 /spl mu/m 4 M/spl times/32 DDR SDRAM show <25 ps peak-to-peak jitter with quiet supply,

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003