Referenced Items are not available for this document.
A low cost high performance register-controlled digital delay-locked loop (DLL) that has novel resolution-enhancing structure with inherent duty cycle correction capability was developed for 1 Gbps×32 DDR SDRAM. Experimental results in a 0.13 μm 4 M×32 DDR SDRAM show <25 ps peak-to-peak jitter with quiet supply, <±2% duty correction from external duty error of ±7%, <150 cycle lock-time, 24 mW at 1.8 V/400 MHz, 60 mW at 2.5 V/500 MHz, and a wide locking range from 66 MHz to over 500 MHz.
Published in:
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Date of Conference: 12-14 June 2003
- Page(s):
- 283 - 284
- Print ISBN:
- 4-89114-034-8
- INSPEC Accession Number:
- 7869164
- Digital Object Identifier :
- 10.1109/VLSIC.2003.1221227
- Product Type:
- Conference Publications
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