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A 90 nm low power 32 K-byte embedded SRAM with gate leakage suppression circuit for mobile applications

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10 Author(s)
K. Nii ; Syst. LSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan ; Y. Tenoh ; T. Yoshizawa ; S. Imaoka
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In sub 100 nm generation, gate tunneling leak current increases and dominates total standby leak current of LSI based on decreasing gate oxide thickness. We propose reducing gate leak current in SRAM using Local DC Level Control (LDLC) and an Automatic Gate Leakage Suppression Driver to reduce gate leak current in the peripheral circuit. We designed and fabricated a 32 KB 1-port SRAM using 90 nm CMOS technology. The 6T-SRAM-cell size is 1.25 /spl mu/m/sup 2/. Evaluation showed that the standby current of 32 KB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003