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3-Transistor antifuse OTP ROM array using standard CMOS process

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2 Author(s)
Jinbong Kim ; Dept. of EECS, KAIST, Taejon, South Korea ; Kwyro Lee

A 3-transistor cell CMOS OTP ROM array using CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003