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A high-speed 128 Kbit MRAM core for future universal memory applications

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15 Author(s)
Bette, A. ; MRAM Dev. Alliance, Infineon Technol., Hopewell Junction, NY, USA ; DeBrosse, J. ; Gogl, D. ; Hoenigschmid, H.
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A 128 Kb MRAM (Magnetic Random Access Memory) test chip has been fabricated utilizing for the first time a 0.18 /spl mu/m, VDD=1.8 V, logic process technology with Cu backend of line. The presented design uses a 1.4 /spl mu/m/sup 2/ ITIMTJ (1-Transistor/1-Magnetic Tunnel Junction) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5 ns random array read access time and random write operations with <5 ns write pulse width.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003