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A process variation compensating technique for sub-90 nm dynamic circuits

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6 Author(s)
Kim, C.H. ; Dept. of ECE, Purdue Univ., West Lafayette, IN, USA ; Roy, K. ; Hsu, S. ; Alvandpour, A.
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A process variation compensating technique for dynamic circuits is described for sub-90 nm technologies where leakage variation is severe. A keeper whose effective strength is optimally programmable based on die leakage enables 10% faster performance, 35% reduction in delay variation, and 5x reduction in robustness failing dies over conventional static keeper design in 90 nm dual-V/sub t/ CMOS.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003