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A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis

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3 Author(s)
Verma, S. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Junfeng Xu ; Lee, T.H.

A frequency-synthesis technique which extracts the N/sup th/ harmonic from an N-stage oscillator is presented. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180/spl deg/-coupled, single-ended three-stage ring oscillators has been fabricated in 0.24 /spl mu/m CMOS, designed to work in the 902-928 MHz ISM band (US and Canada). It provides two outputs: one at the normal operating frequency of the oscillator, and another at three times that frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 /spl mu/A of current.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003