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A design of a compact 2 GHz-PLL with a new adaptive active loop filter circuit

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3 Author(s)
M. Toyama ; Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan ; S. Dosho ; N. Yanagisawa

This paper describes a design of a compact active loop filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using the new loop filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of the reference clock. Moreover, the new LPF can decrease the capacitance value to 1/10-1/20 of conventional one. A test chip was fabricated in 0.15 /spl mu/m-CMOS process. The total chip area of the PLL is reduced to 1/2 of previous one. The jitter performance is almost equal to conventionally biased PLL.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003