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We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to meet several important requirements, such as small size, low power, low cost and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a baseband processor, such as SoC., in a GPS receiver. The GPS chip, with a total size of 6.4/spl times/6.4 mm, contains a 2.3/spl times/2.0 mm radio part, including RF front end, PLLs, IF functions, and 500 K gates of baseband logic, including mask ROM, SRAM and Dual Port SRAM. It's fabricated using 0.18-/spl mu/m CMOS Technology with a MIM option and operates from a 1.6 to 2.0-V power supply. Experimental results show a very low power consumption of, typically, 57-mW for a fully functional chip including baseband, and a high sensitivity of -150 dBm. Through countermeasures for substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external LNA.